Recently, memory devices have been developed that include bank structures. Bank structures can logically divide a memory device into different portions that can be accessed when selected. A bank typically includes one or more memory cell arrays that can be accessed in a row-wise direction by a row decoder. One drawback associated with memory devices having bank structures is that in order to access banks separately, a row decoder is associated with each bank. Row decoders, particularly for large capacity memory devices, can consume considerable area. Increases in device area may result in more expensive manufacturing costs.
To better understand the drawbacks associated with conventional bank structure memories, an example of a conventional memory device is set forth in FIG. 5. FIG. 5 illustrates a synchronous dynamic random access memory (SDRAM) having multiple banks, where each bank is controlled by a corresponding row decoder. The approach set forth in FIG. 5 is disclosed in Japanese Patent Application Laid-open No. Hei 9-231755. The SDRAM of FIG. 5 can be formed on a semiconductor substrate, such as a monocrystalline silicon substrate, using known semiconductor integrated circuit manufacturing techniques.
Referring now to FIG. 5, the conventional SDRAM is designated by the general reference character 500, and is shown to include a memory array 502-A that includes a memory bank 0 (shown as "BANK 0"), and a memory array 502-B that includes a memory bank 1 (shown as "BANK 1"). Each memory array (502-A and 502-B) includes DRAM memory cells arranged in a matrix. Each memory cell includes a select terminal and a data input/output (I/O) terminal. Memory cells within the same row have select terminals coupled to a common word line (not shown). Memory cells within the same column have data I/O terminals coupled to a complementary data line (also not shown).
A word line of memory array 502-A can be driven to a select level by a mat control circuit 504-A and row decoder 506-A. The mat control circuit 504-A and row decoder 506-A can decode a row address, and in conjunction with a row timing signal, drive a selected word line to a select level.
The complementary data lines of memory array 502-A are coupled to a sense amplifier and column select circuit 508-A. Sense amplifiers within the sense amplifier and column select circuit 508-A can detect fine potential differences on respective complementary data lines by amplifying such potential differences. In this manner, data can be read from selected memory cells. The sense amplifier and column select circuit 508-A includes switch circuits for selecting predetermined complementary data lines, and coupling them to a complementary common data I/O bus 512. The switch circuits selects predetermined complementary data lines according to a decoded column address. Column addresses for memory array 502-A are decoded by a column decoder 510-A.
In a similar arrangement to memory array 502-A, the memory array 502-B is provided with a mat control circuit 504-B, a row decoder 506-B, a sense amplifier and column select circuit 508-B, and a column decoder 510-B.
The complementary common data I/O bus 512 is shown to be coupled to both sense amplifier and column select circuits (508-A and 508-B). The complementary common data I/O bus 512 is further connected to the output of an input buffer 514 and to the input of an output buffer 516. The input buffer 514 receives input values from data I/O terminals I/O0-I/O7. Similarly, the output buffer 516 can place output values on the data I/O terminals I/O0-I/O7.
The SDRAM 500 of FIG. 5 receives address values in a multiplexed fashion. Initially a row address can be applied via address input terminals A0 to A11. The row address is latched in a row address buffer 518. Subsequently, a column address can be applied via address input terminals A0 to A11 and latched in a column address buffer 520. In the arrangement of FIG. 5, the row address buffer 518 holds a latched row address for one clock cycle of a master clock CLK. This is in contrast to other conventional approaches in which a row address is latched for an entire memory cycle. In contrast, the column address buffer 520 of FIG. 5 latches a column address during an entire memory cycle.
As shown in FIG. 5, the row address buffer 518 can also receive a refresh address from a refresh counter 522 in a refresh mode of operation. The column address buffer 520 provides column address values to a column address counter 524. The column address counter 524 provides select data to the column decoders (510-A and 510-B).
The SDRAM 500 further sets forth a controller 526. The controller is supplied with external control signals, such as a master clock signal CLK, a clock enable signal CKE, a chip select signal /CS, a column address strobe signal /CAS, a row address strobe signal /RAS, a write enable signal /WE, and data I/O mask control signal DQM. The controller 526 also receives control data by way of address terminal A11. It is understood that those signals that are preceded by the symbol "/" are active when at a logic low.
In response to the various input values (CLK, CKE, /CS, /CAS, /RAS, /WE, DQM, and A11) the controller 526 generates a number of internal timing signals, shown as XDGL0, XDGL1, XDP0, XDPO1, etc. The internal timing signals control the operation mode of the SDRAM 500 and the operation of the various circuit blocks set forth in FIG. 5. Accordingly, the controller 526 includes control logic and a mode register for generating the appropriate internal timing signals.
It is noted that the CLK signal is the master clock for the SDRAM 500. As a result, the other external input signals are significant on the rising edge of the CLK signal. It is further noted that the chip select signal /CS initiates the start of a command input cycle by transitioning to a low logic level.
As described above, in the conventional example of FIG. 5 each of the banks (BANK0 and BANK1) is provided with a row decoder (506-A and 506-B) and a column decoder (510-A and 510-B) in order to allow each bank (BANK0 and BANK1) to be accessed individually in a read or write operation.
A conventional DRAM having a multi-bank structure that includes sub-array plates will now be described with reference to FIG. 6. Referring now to FIG. 6, a portion of a DRAM structure having sub-array plates is designated by the general reference character 600. The DRAM structure 600 includes sub-array plates 602-A and 602-B having memory cells that are accessed by way of complementary main word lines MWL and /MWL. The complementary main word lines (MWL and /MWL) are coupled to memory cells within the sub-array plates (602-A and 602-B) in the row-wise direction through a number of sub-array word lines (SWL-00 to SWL-13). This arrangement results in a hierarchical structure in which eight rows of sub-array word lines are controlled by a pair of complementary main word lines (MWL and /MWL).
Sub-array word lines drivers are shown as 604-00 to 604-13, and drive sub-array word lines SWL-00 to SWL-13, respectively. Each sub-array word line driver (604-00 to 604-13) receives the complementary main word line signals (WL and /WL), as well as one of eight word line supply signals RX00 to RX13. In addition, each sub-array word line driver (604-00 to 604-13) also receives a pass voltage VDH.
The arrangement of FIG. 6 thus includes a row decoder and main word line driver to generate the complementary main word line signals (MWL and /MWL) for eight rows of memory cells. In addition, drivers may be provided to generate the word line supply signals (RX00 to RX13) according to certain address values.
In the structure of FIG. 6, to access a row of memory cells, the complementary main word line pair and one word line supply signal are selected. In this arrangement, the selected complementary main word line pair will couple the selected word line supply signal to a sub-array word line.
The operation of the structure set forth in FIG. 6 will now be described in conjunction with a timing diagram set forth in FIG. 7. The timing diagram illustrates various waveforms for signals set forth in FIG. 6. Waveform "MWL, /MWL" illustrates the response of the complementary main word lines (MWL and /MWL). Waveform RXmn illustrates the response of the RX00 to RX13 signals. Waveform SWLmn illustrates the response of sub-array word lines SWL-00 to SWL-13. FIG. 7 illustrates the selection of sub-array word line SWL-00 followed by the selection of sub-array word line SWL-10. Also included in FIG. 7 are various logic level values, including a low supply value GND, a high supply value VDD and higher supply value VDH.
At time t0, the MWL signal transitions to the VDH level, while the complementary /MWL signal transitions to the low level. Shortly thereafter, the RX00 signal transitions to the VDH level. As a result, the sub-array word line SWL-00 is selected and driven to a high VDH level. At time t1 the MWL signal returns low while the /MWL signal rises to the VDD level. At about the same time, the RX00 signal returns to the GND level. As a result, the sub-array word line SWL-00 is de-selected, and returns to the GND level.
At time t2, the MWL signal transitions once again to the VDH level, while the complementary /MWL signal transitions to the low level once again. Shortly thereafter, the RX10 signal transitions to the VDH level. As a result, the sub-array word line SWL-10 is selected and driven to a high VDH level. At time t3 the MWL signal returns low while the /MWL signal rises to the VDD level. At about the same time, the RX10 signal returns to the GND level. As a result, the sub-array word line SWL-10 is de-selected, and returns to the GND level.
In this way, because a sub-array plate is selected for each bank, a circuit for controlling the various sub-array word line drivers (604-00 to 604-13) may be required for each bank. The same general circuit for sub-array word lines is disclosed in "Advanced Electronics I-9", "Super LSI memory", p.160, issued by Baifukan.
A drawback to conventional multi-bank memory device approaches is the amount of area that may be consumed by providing a row decoder for each bank. Increases in bank size or the overall number of banks may result in corresponding increases in circuit area for row decoders.
Another drawback to conventional approaches having sub-array plates, such as that set forth in FIG. 6, is the limited control of sub-array word lines. Because the complementary main word lines (MWL and /MWL) are common to both sub-array plates (602-A and 602-B), sub-array word lines in different sub-array plates cannot be controlled individually. Consequently, if it is desired to have separately controllable sub-array plates, an additional complementary main word line pair may be needed for each sub-array plate. Such an approach may not be possible due to allowable conductive line pitch and/or may require additional conductive layers. This can make the layout of the device more complex and/or the fabrication of the device more expensive.
Another aspect of integrated circuits is the number of conductive lines required to provide necessary signals to the various portions of the device. In particular, the "pitch" (or minimum spacing) required for conductive lines may be of particular concern for memory devices. Memory devices typically include memory cells of very small size. Accordingly, the word lines and/or bit lines connected to the memory cells usually have as small a pitch as is practicable. Minimum pitch requirements can also be of concern for higher levels of metallization. For example, in the circuit of FIG. 6, it is important not only for the sub-array word lines to have a small pitch, but also for the main word lines to have a small pitch.
Reducing the number of conductive lines in a memory device can also be desirable in that it may result in more efficient routing of signals.